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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>FMLA (by element) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">FMLA (by element)</h2>
      <p class="aml">Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&amp;FP register by the specified value in the second source SIMD&amp;FP register, and accumulates the results in the vector elements of the destination SIMD&amp;FP register. All the values in this instruction are floating-point values.</p>
      <p class="aml">This instruction can generate a floating-point exception. Depending on the settings in <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>, the exception results in either a flag being set in <a class="armarm-xref" title="Reference to Armv8 ARM section">FPSR</a> or a synchronous exception being generated. For more information, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Floating-point exception traps</a>.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 4 classes:
      <a href="#iclass_2reg_scalar_half">Scalar, half-precision</a>
      , 
      <a href="#iclass_2reg_scalar_single_and_double">Scalar, single-precision and double-precision</a>
      , 
      <a href="#iclass_2reg_element_half">Vector, half-precision</a>
       and 
      <a href="#iclass_2reg_element_single_and_double">Vector, single-precision and double-precision</a>
    </p>
    <h3 class="classheading"><a id="iclass_2reg_scalar_half"/>Scalar, half-precision<span style="font-size:smaller;"><br/>(FEAT_FP16)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">L</td><td class="lr">M</td><td colspan="4" class="lr">Rm</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="lr">H</td><td class="lr">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td colspan="2"/><td/><td colspan="5"/><td colspan="2"/><td/><td/><td colspan="4"/><td/><td class="droppedname">o2</td><td colspan="2"/><td/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="FMLA_asisdelem_RH_H"/><p class="asm-code">FMLA  <a href="#sa_hd" title="16-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Hd&gt;</a>, <a href="#sa_hn" title="First 16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a>, <a href="#sa_vm" title="Second SIMD&amp;FP source register [V0-V15] (field &quot;Rm&quot;)">&lt;Vm&gt;</a>.H[<a href="#sa_index" title="Element index [0-7] (field &quot;H:L:M&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveFP16Ext.0" title="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;

integer idxdsize = if H == '1' then 128 else 64;
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H:L:M);

integer esize = 16;
integer datasize = esize;
integer elements = 1;
boolean sub_op = (o2 == '1');</p>
    <h3 class="classheading"><a id="iclass_2reg_scalar_single_and_double"/>Scalar, single-precision and double-precision</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr">sz</td><td class="lr">L</td><td class="lr">M</td><td colspan="4" class="lr">Rm</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="lr">H</td><td class="lr">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td/><td colspan="4"/><td/><td class="droppedname">o2</td><td colspan="2"/><td/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="FMLA_asisdelem_R_SD"/><p class="asm-code">FMLA  <a href="#sa_v" title="Width specifier (field &quot;sz&quot;) [D,S]">&lt;V&gt;</a><a href="#sa_d" title="SIMD&amp;FP destination register number (field &quot;Rd&quot;)">&lt;d&gt;</a>, <a href="#sa_v" title="Width specifier (field &quot;sz&quot;) [D,S]">&lt;V&gt;</a><a href="#sa_n" title="First SIMD&amp;FP source register number (field &quot;Rn&quot;)">&lt;n&gt;</a>, <a href="#sa_vm_1" title="Second SIMD&amp;FP source register (field &quot;M:Rm&quot;)">&lt;Vm&gt;</a>.<a href="#sa_ts" title="Element size specifier (field &quot;sz&quot;) [D,S]">&lt;Ts&gt;</a>[<a href="#sa_index_1" title="Element index (field &quot;sz:L:H&quot;) [H,H:L]">&lt;index&gt;</a>]</p></div><p class="pseudocode">integer idxdsize = if H == '1' then 128 else 64;
integer index;
bit Rmhi = M;
case sz:L of
    when '0x' index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H:L);
    when '10' index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H);
    when '11' UNDEFINED;

integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rmhi:Rm);

integer esize = 32 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer datasize = esize;
integer elements = 1;
boolean sub_op = (o2 == '1');</p>
    <h3 class="classheading"><a id="iclass_2reg_element_half"/>Vector, half-precision<span style="font-size:smaller;"><br/>(FEAT_FP16)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">0</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">L</td><td class="lr">M</td><td colspan="4" class="lr">Rm</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="lr">H</td><td class="lr">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td/><td/><td colspan="5"/><td colspan="2"/><td/><td/><td colspan="4"/><td/><td class="droppedname">o2</td><td colspan="2"/><td/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="FMLA_asimdelem_RH_H"/><p class="asm-code">FMLA  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;Q&quot;)">&lt;T&gt;</a>, <a href="#sa_vn" title="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;Q&quot;)">&lt;T&gt;</a>, <a href="#sa_vm" title="Second SIMD&amp;FP source register [V0-V15] (field &quot;Rm&quot;)">&lt;Vm&gt;</a>.H[<a href="#sa_index" title="Element index [0-7] (field &quot;H:L:M&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveFP16Ext.0" title="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;

integer idxdsize = if H == '1' then 128 else 64;
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H:L:M);

integer esize = 16;
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
boolean sub_op = (o2 == '1');</p>
    <h3 class="classheading"><a id="iclass_2reg_element_single_and_double"/>Vector, single-precision and double-precision</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">0</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr">sz</td><td class="lr">L</td><td class="lr">M</td><td colspan="4" class="lr">Rm</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="lr">H</td><td class="lr">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td/><td/><td colspan="5"/><td/><td/><td/><td/><td colspan="4"/><td/><td class="droppedname">o2</td><td colspan="2"/><td/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="FMLA_asimdelem_R_SD"/><p class="asm-code">FMLA  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t_1" title="Arrangement specifier (field &quot;Q:sz&quot;) [2D,2S,4S]">&lt;T&gt;</a>, <a href="#sa_vn" title="First SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a>.<a href="#sa_t_1" title="Arrangement specifier (field &quot;Q:sz&quot;) [2D,2S,4S]">&lt;T&gt;</a>, <a href="#sa_vm_1" title="Second SIMD&amp;FP source register (field &quot;M:Rm&quot;)">&lt;Vm&gt;</a>.<a href="#sa_ts" title="Element size specifier (field &quot;sz&quot;) [D,S]">&lt;Ts&gt;</a>[<a href="#sa_index_1" title="Element index (field &quot;sz:L:H&quot;) [H,H:L]">&lt;index&gt;</a>]</p></div><p class="pseudocode">integer idxdsize = if H == '1' then 128 else 64;
integer index;
bit Rmhi = M;
case sz:L of
    when '0x' index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H:L);
    when '10' index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(H);
    when '11' UNDEFINED;

integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rmhi:Rm);

if sz:Q == '10' then UNDEFINED;
integer esize = 32 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
boolean sub_op = (o2 == '1');</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Hd&gt;</td><td><a id="sa_hd"/>
        
          <p class="aml">Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Hn&gt;</td><td><a id="sa_hn"/>
        
          <p class="aml">Is the 16-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;V&gt;</td><td><a id="sa_v"/>
        <p>Is a width specifier, 
      encoded in
      <q>sz</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">sz</th>
                <th class="symbol">&lt;V&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;d&gt;</td><td><a id="sa_d"/>
        
          <p class="aml">Is the number of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;n&gt;</td><td><a id="sa_n"/>
        
          <p class="aml">Is the number of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vd&gt;</td><td><a id="sa_vd"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t"/>
        <p>For the half-precision variant: is an arrangement specifier, 
      encoded in
      <q>Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">4H</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">8H</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr><tr><td/><td><a id="sa_t_1"/>
        <p>For the single-precision and double-precision variant: is an arrangement specifier, 
      encoded in
      <q>Q:sz</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">Q</th>
                <th class="bitfield">sz</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">0</td>
                <td class="symbol">2S</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">1</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="bitfield">0</td>
                <td class="symbol">4S</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="bitfield">1</td>
                <td class="symbol">2D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vn&gt;</td><td><a id="sa_vn"/>
        
          <p class="aml">Is the name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vm&gt;</td><td><a id="sa_vm"/>
        
          
        
        
          <p class="aml">For the half-precision variant: is the name of the second SIMD&amp;FP source register, in the range V0 to V15, encoded in the "Rm" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_vm_1"/>
        
          
        
        
          <p class="aml">For the single-precision and double-precision variant: is the name of the second SIMD&amp;FP source register, encoded in the "M:Rm" fields.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ts&gt;</td><td><a id="sa_ts"/>
        <p>Is an element size specifier, 
      encoded in
      <q>sz</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">sz</th>
                <th class="symbol">&lt;Ts&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;index&gt;</td><td><a id="sa_index"/>
        
          
        
        
          <p class="aml">For the half-precision variant: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.</p>
        
      </td></tr><tr><td/><td><a id="sa_index_1"/>
        <p>For the single-precision and double-precision variant: is the element index, 
      encoded in
      <q>sz:L:H</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">sz</th>
                <th class="bitfield">L</th>
                <th class="symbol">&lt;index&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">x</td>
                <td class="symbol">H:L</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="bitfield">0</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="bitfield">1</td>
                <td class="symbol">RESERVED</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize) operand1 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(idxdsize) operand2 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[m, idxdsize];
bits(datasize) operand3 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
bits(esize) element1;
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize];
<a href="shared_pseudocode.html#FPCRType" title="type FPCRType">FPCRType</a> fpcr = FPCR[];
boolean merge = elements == 1 &amp;&amp; <a href="shared_pseudocode.html#impl-shared.IsMerging.1" title="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
bits(128) result = if merge then <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(128);

for e = 0 to elements-1
    element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
    if sub_op then element1 = <a href="shared_pseudocode.html#impl-shared.FPNeg.1" title="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
    <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.FPMulAdd.4" title="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, fpcr);

<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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